1. Field of the Invention
The present invention relates to bus circuits and operating methods thereof, and more particularly, to a bus circuit for transmitting information to one another between a plurality of functional portions, and operating methods thereof.
2. Description of the Background Art
FIG. 13 shows a conventional precharge-type bus circuit. This type of bus circuit is used, for example, in semiconductor integrated circuit devices such as microcomputers. In FIG. 13, a bus interconnection 1 is connected to a power supply terminal 3 through a precharging P-channel MOS transistor 2. The transistor 2 has a source connected to the power supply terminal 3, a drain connected to the bus interconnection 1, and a gate receiving a precharging signal T.sub.PC. A plurality of circuit blocks 11a to 11d are connected to the bus interconnection 1. Each of the circuit blocks 11a to 11d comprises latch circuits 4 and 5, a logic circuit 6 and a bus driver 7. Information from the bus interconnection 1 is inputted to the latch circuit 4. Output of the latch circuit 4 is applied to the logic circuit 6, output of which is applied to the latch circuit 5. Information outputted from the latch circuit 5 is applied to the bus interconnection 1 through the bus driver 7. Each of the circuit blocks 11a to 11d functions as a source (transmitting portion) and a destination (receiving portion).
In FIG. 14, there is mainly shown a detailed circuit structure of the circuit block 11a. The latch circuit 4 comprises inverters 41, 42 and 43, a NAND gate 44 and N-channel MOS transistors 45 and 46. One input terminal of the NAND gate 44 receives a control signal T1 and the other receives a selecting signal S1a. When the selecting signal S1a is at the "H" level, the circuit block 11a is selected as a destination. When the control signal T1 attains the "H" level, the transistor 45 is turned on so that information on the bus interconnection 1 is inputted to the input terminal of the inverter 41. When the control signal T1 falls down to the "L" level, the transistor 46 is turned on so that the information is latched in the latch portion comprising the inverters 41 and 42, and the transistor 46.
Output of the latch circuit 4 is inputted to the logic circuit 6, a portion for performing processings such as logic operation. Output of the logic circuit 6 is inputted to the latch circuit 5.
The latch circuit 5 comprises inverters 51, 52 and 53 and N-channel MOS transistors 54 and 55. The gate of the transistor 54 receives a control signal T2. The control signal T2 is also applied to the gate of the transistor 55 through the inverter 53. When the control signal T2 attains the "H" level, the transistor 54 is turned on so that the information from the logic circuit 6 is applied to the input terminal of the inverter 51. When the control signal T2 falls down to the "L" level, the transistor 55 is turned on so that the information is latched in a latch portion comprising the inverters 51 and 52 and the transistor 55.
The bus driver 7 comprises an AND gate 71 and N-channel MOS transistors 72 and 73. The gate of the transistor 73 receives output from the latch circuit 5. One input terminal of the NAND gate 71 receives a control and the other receives a selecting signal S2a. signal T.sub.BS and the other receives a selecting signal S2a. When the selecting signal S2a is at the "H" level, the circuit block 11a is selected as a source. When the control signal T.sub.BS attains the "H" level, an inverted signal of output from the latch circuit 5 is applied to the bus interconnection 1.
The other circuit blocks 11b to 11d are configured in the same way as the circuit block 11a. The circuit blocks 11b to 11d receive, however, selecting signals S1b and S2b to S1d and S2d, respectively, instead of the selecting signals S1a and S2a.
A description will be now made on operation of the bus circuit shown in FIGS. 13 and 14 with reference to a timing chart of FIG. 15. A case in which data latched in the latch circuit 5 of the circuit block 11a should be transferred to the latch circuit 4 of the circuit block 11d will be here taken as an example. This means that the circuit block 11a is a source and the circuit block 11d is a destination in this case.
In FIG. 15, the time duration from t0 to t4 constitutes a single transfer cycle. Initially, the control signal T.sub.BS falls to the "L" level and then the precharge signal T.sub.PC falls to the "L" level, which turns the transistor 2 on so that current flows from the power supply terminal 3 to the bus interconnection 1, raising potential on the bus interconnection to the "H" level. At this moment, the selecting signals S1a to S1d and S2a to S2d are at the "L" level. The control signal T2 attains in turn the "H" level at the time of t1. This permits the latch circuit 5 to accept output from the logic circuit 6. Subsequently, the selecting signals S2a and S1d attain the "H" level, which allows selection of the circuit block 11a as a source and the circuit block 11d as a destination.
At the time t2, the precharge signal T.sub.PC attains the "H" level, turning the transistor 2 off. As a result, the bus interconnection 1 is held at the "H" level. At this moment, the control signal T2 falls to the "L" level, which causes the data having been applied to the latch circuit 5 to be held therein and then outputted. When the control signal T.sub.BS rises to the "H" level, the bus driver 7 in the circuit block 11a is activated. If the data outputted from the latch circuit 5 is at the "H" level, the potential on the bus interconnection 1 slowly returns to the "L" level. Conversely, if the data outputted from the latch circuit 5 is at the "L" level, the potential on the bus interconnection 1 remains held at the "H" level. In other words, inverted ones of the data latched in the latch circuit 5 are applied to the bus interconnection 1.
At the time of t3, the control signal T1 rises to the "H" level, which permits the latch circuit 4 in the circuit block 11d to accept the data on the bus interconnection 1. When the control signal T1 falls to the "L" level at the time t4, the data having been applied to the latch circuit 4 is latched therein and then outputted.
As described in the foregoing, data outputted from the logic circuit of the circuit block 11a are transmitted to the logic circuit 6 of the circuit block 11d.
In conventional precharge-type bus circuits, any increased number of circuit blocks to be selected as source and destination of a bus has required a longer interconnection and larger capacitance for the bus, and also an increased number of bus drivers. Consequently, there have been problems such as too much time to be taken in charging and discharging the bus interconnection.